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IBM Cloud: Article

Predictive Failure Analytics with Optimization for Big Data

Applying data mining and advanced statistical methods to analyze, diagnose and improve manufacturing yield

The predictive statistical analysis capability is tightly integrated into a framework that provides other diagnostics such as the ability to explore sensitivities of the circuit to yield and optimize the tradeoffs of circuit performance and yield. This allows the designer to explore failure corners, run advanced sensitivity analysis, iterate to improve the design and then re-run failure corners to validate that the targeted yield improvements have been achieved. Figure 9 shows the capability to run sensitivity analysis on failed/saved corners.

Figure 9: Ability to run sensitivity analysis to find areas to improve design yield

When a foundry develops a new process technology there is significant effort in ensuring that the process will deliver high yields. SRAM designs are typically used as a yield verification vehicle. Manufacturing and validating SRAM yields via silicon runs is certainly feasible but extremely costly and time consuming. As an alternative or supplement, predictive failure analytics are being used to analyze critical SRAM performance measures such as read current (Iread), read/write margins and to determine the impact of process variations on the functional yield. Process splits and related device parameter variations can be used to study their impact on the key SRAM performance measures using high sigma analysis to determine what the yield boundary may look like, and to provide guidance to process engineers to fine tune the process to achieve an optimum yield. The example given in Figure 10 shows the high sigma SRAM yield analysis results in a contour plot as a function of different parameters which process engineers can tune. The user can also run a trend analysis to indicate which direction the yield can be improved. Silicon runs with split lots can then be used to validate the high sigma analysis results. Setting up such a methodology enables a foundry to augment their silicon yield validation program with a much faster high sigma sampling and simulation based technique. The recent success of our predictive failure analytics tool in a leading foundry has proved its value in significantly reducing the development time for SRAM yield ramp for a leading edge process technology.

Figure 10: High sigma SRAM yield analysis contour as a function of Vth_lin (pull up transistor) and Vth_sat (pull down transistor);

High sigma SRAM yield trend as a function of Vth variation of the pull down transistor.

Another foundry use case is for SRAM cell characterization during the early process development stage (Figure 11). For example, if a new device type such as FinFET is being developed it is useful to verify the robustness of the SRAM cell under different environmental conditions or process variation. Figure 11 shows such a high sigma analysis where the SNM characterization capability is used to verify that the FinFET SRAM cell has good Vdd scaling. The figure also shows how yield versus instance parameter variation (such as Tfin, Hfin, L) out in the tails of the performance distribution can be studied very early during the process development cycle (pre-silicon).

Figure 11: FinFET SRAM characterization - SNM Vdd scaling, Instance parameter variation vs. yield impact at high sigma values.

Libraries are part of the basic building block elements required prior to initiating the design of more complex SoCs. Library groups start development very early in the lifecycle of a new process, often working with multiple versions of the process design kit (PDK) provided by the foundry. Library groups are tasked with developing designs that will typically be repeated several to as many as millions of times in a SoC which makes their designs ideal candidates for high sigma analysis due to the need to verify yields out to very high sigma values. Yield characterization of these types of designs requires many simulations and possibly multiple iterations as the PDK revises up. Hence, high speed predictive failure analytics are an invaluable tool to reduce time, simulation license costs and provide superior accuracy compared to ad hoc approaches. Figure 12 shows a summary of several cases where predictive failure analytics have been used to characterize library circuit components, including an SRAM array, an IO block and a filter array.

Figure 12: High dimension cases run by library groups at advanced process nodes

In addition to some of the cases shown in this paper, predictive failure analytics are ideally suited to other repetitive digital structures which may have high replication rates on the chip, such as standard cells, decoder circuits, hit logic, flip flops, dynamic latches, etc.

Analog circuits are typically not instantiated a very large number of times in a SoC's and hence are usually analyzed out to 3s. However in cases where tight bit-error-rate (BER) and jitter budgets (ex: for Fibre Channel) require design margins out to high sigma, an extremely long simulation run would be required which means that it is impractical to couple this with a large number of Monte Carlo samples. Similar to the case described above for HSIO, analog circuits for medical, automotive, military and aerospace applications also typically have high sigma design requirements. All of these applications are a good candidate for high sigma predictive failure analysis.

Conclusion
In this article we have reviewed some of the basic concepts of predictive failure analytics including how process variations are classified and modeled, and how it is taken into account during the design and manufacturing process for integrated circuits.

The key value proposition delivered by high sigma predictive failure analytics are as follows:

  • Accuracy: Reliable and accurate high sigma analysis method attributed to its Monte Carlo nature. Extensive hardware validation by different applications at various advanced process nodes.
  • Productivity: Massive improvement in yield analysis turn-around time over traditional Monte Carlo for 4-5s designs. Makes 7s+ yield analysis practical with fast high sigma analysis. Ease of use of the product enables rapid adoption.
  • Scalability: Viability to analyze larger designs such as SRAM arrays and I/O circuits that may require >10K variables for high sigma analysis.
  • 9s+ Yield Analysis and Optimization: Reliable and accurate method that allows designers to analyze yield out to very high sigma (9s+) values for high dimension cases. DFY flow integration enables yield vs. power, performance, area (PPA) trade-offs to improve design robustness and optimize yield.
  • Parallelization on farms & cloud: Simplified parallelization model makes high sigma yield analysis scalable to large dimension and large scale problems, and ease of adaption to cloud computing could makes it a cost-effective solution for many diverse applications.

Acknowledgment

The authors would like to acknowledge IBM management, V. Zyuban, Jeff Burns for their support and Proplus management.

References

  1. R. V. Joshi, " Low power design for nanoscale era," Key note Talk, ISOC, 2013.
  2. R. V. Joshi, R. Kanj. A. Pelella, A. Tuminaro, Y. Chan," The Dawn of Predictive Chip Yield Design- Along and Beyond the Memory Lane," IEEE Design & Test of Computers, Dec 2010.
  3. R. Joshi, R. Kanj, S. Butt, E. Acar, D. Lea, D. Sciacca," Hardware corroborated variability aware design," VLSI Design Conference, 2013, pp.344-349.
  4. R. Kanj, R. V. Joshi, S. Nassif,"Mixture Importance Sampling and Its Application to the Analysis of SRAM Designs in the Presence of Rare Failure Events," Proc. 43rd Design Automation Conf 2006, pp. 69-72.
  5. Rajiv Joshi, Rouwaida Kanj, Sani Nassif, Donald Plass, Yuen Chan, Ching-Te Chuang," Statistical Exploration of the Dual Supply Voltage Space of a 65nm PD/SOI CMOS SRAM Cell," ESSDERC 2006, pp. 315-318.
  6. C. Visweswariah, "Statistical Techniques to Achieve Robustness and Quality" ISQED 2008, pp. 568.
  7. E. Fluhr et al.," POWER8 A 12 core server class processor in 22nm SOI with 7.6Tbs offchip bandwidth," Proc. of ISSCC, 2014, pp.96-97.

More Stories By Rajiv V. Joshi

Dr. Rajiv V. Joshi is a research staff member at T. J. Watson research center, IBM. He received his B.Tech I.I.T (Bombay, India), M.S (M.I.T) and Dr. Eng. Sc. (Columbia University). His novel interconnects processes and structures for aluminum, tungsten and copper technologies which are widely used in IBM for various technologies from sub-0.5μm to 14nm. He has led successfully pervasive statistical methodology for yield prediction and also the technology-driven SRAM at IBM Server Group. He commercialized these techniques. He received 3 Outstanding Technical Achievement (OTAs), 3 highest Corporate Patent Portfolio awards for licensing contributions, holds 54 invention plateaus and has over 200 US patents and over 350 including international patents.

Dr. Joshi has authored and co-authored over 175 papers. He is a recipient of 2013 IEEE CAS Industrial Pioneer award and 2013 Mehboob Khan Award from Semiconductor Research corporation. He is Distinguished Lecturer for IEEE CAS and EDS society. He is IEEE and ISQED fellow and distinguished alumnus of IIT Bombay. He serves as an Associate Editor of TVLSI. He served on committees of ISLPED (Int. Symposium Low Power Electronic Design), IEEE VLSI design, IEEE CICC, IEEE Int. SOI conf ISQED and Advanced Metallization Program committees. He is an industry liaison for universities as a part of the Semiconductor Research Corporation.

More Stories By Bruce W. McGaughy

Dr. Bruce W. McGaughy is a Distinguished Engineer, Simulation Chief Architect. He received a BS in Electrical Engineering from the University of Illinois at Urbana/Champaign and an MS and PhD in Electrical Engineering and Computer Science from the University of California at Berkeley, in 1994, 1995 and 1997, respectively. He has conducted and published research in the fields of circuit simulation, device physics, reliability, electronic design automation, computer architecture and fault tolerant computing. Prior to his current assignment, he worked for Integrated Device Technolgy (IDT), Siemens, Intel, Berkeley Technology Associates, and Celestry. In 2003, Dr. McGaughy was the group director in charge of circuit simulation R&D at Cadence, including Spectre, SpectreRF and UltraSim.

In 2006, Dr. McGaughy became the distinguished engineer and chief architect for Cadence simulation products, including Spectre, SpectreRF, UltraSim and AMS Designer. In 2008, he joined ProPlus Design Solutions as the Senior VP of Engineering and Chief Technology Officer. He is in charge of all of ProPlus R&D efforts, including the BsimProPlus model extraction platform, the NanoSpice parallel spice simulator, and the NanoYield DFY platform.

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